Cadence SP&R Design Technology Integrated in Toshiba ASIC Design Flow

SAN JOSE, Calif.--(BUSINESS WIRE)--Nov. 7, 2001--Cadence Design Systems, Inc. (NYSE:CDN - news), the world's leading supplier of electronic design products and services, announced today that Toshiba America Electronic Components, Inc. (TAEC) has integrated Cadence® SP&R (synthesis/place-and-route) design technology in its MegaGate TDF(TM) application specific integrated circuit (ASIC) design flow. Due to the timing closure predictability of Cadence technology, TAEC chose Cadence SP&R with Physically Knowledgeable Synthesis (PKS) for its production flows.

"TAEC is committed to providing its ASIC customers with tighter links between logical and physical design processes to further enable designers to optimize their high-performance deep sub-micron chips," said Jeff Berkman, senior vice president of SLI Engineering at TAEC. "SP&R broadens our TDF design flow with the latest technology from Cadence. Our production-proven hierarchical design flow tightly links top-down design planning with SP&R to shorten the design cycle time and allow our customers to increase timing closure predictability and achieve on-spec, on-time delivery."

Shrinking process geometries have made timing closure a serious consideration for designers choosing ASIC vendors. With PKS in the TAEC design kit, designers using Cadence technologies can achieve tight correlation with final routed results because PKS integrates synthesis, timing and placement, and true global routing engines in one solution.

"Earlier this year, TAEC announced a static timing design kit employing BuildGates® synthesis technology in its ASIC design flows," said John Murphy, vice president, Cadence SP&R. "We are pleased that TAEC now supports PKS in its design kit. This provides TAEC customers with a Cadence design environment that delivers early predictability and rapid timing closure coupled with superior performance, and sign-off quality results."

About Cadence SP&R

Cadence SP&R is the industry's first unified synthesis/place-and-route system. It consists of PKS physical synthesis and Silicon Ensemble® -PKS (SE-PKS) optimization place-and-route. SP&R features correlation within three percent through common timing, synthesis, placement, and routing engines used by both logic designers and physical designers.

Pricing and Availability

PKS synthesis products are available worldwide for UNIX-based workstations from Hewlett-Packard and Sun Microsystems, and for AIX-based workstations from IBM. One-year U.S. list prices start at $100,000. For information on international pricing, please contact the local Cadence sales office.

About Cadence

Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,700 employees and 2000 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products, and services is available at www.cadence.com.

Note to Editors: Cadence, the Cadence logo, BuildGates and Silicon Ensemble are registered trademarks of Cadence Design Systems, Inc. MegaGate TDF is a trademark of Toshiba America Electronic Components, Inc. All other trademarks are the property of their respective owners.

     Cadence Design Systems, Inc.
     Parvesh Bal-Sandhu, 408/894-2512
     parvesh@cadence.com
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     Matt McGinnis, 503/672-4689
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